This invention relates generally to tools for computer-aided verification engineering. More specifically, the present invention relates to a technique for logic design verification using register transfer language (RTL).
Electronic design automation (“EDA”) is becoming increasingly complicated and time consuming, due in part to the greatly increasing size and complexity of the electronic devices designed by EDA tools. Such devices include general purpose microprocessors as well as custom logic devices including programmable logic devices (PLDs) and ASICS.
A typical programmable logic device (PLD) contains many logic array blocks (LABs) arranged in a two-dimensional array. Additionally, PLDs have an array of intersecting signal conductors for programmably selecting and conducting logic signals to, from, and between the logic array blocks. LABs contain a number of programmable logic elements (LEs) which provide relatively elementary logic functions such as NAND, NOR, and exclusive OR. Each LAB also includes a plurality of programmable memory bits, i.e. configuration RAM bits (“CRAMs”), used to program the LAB. CRAM can be implemented as an EPROM, EEPROM, fuse, anti-fuse, SRAM, MRAM, FRAM, DRAM or the like.
Typically, the circuit designer uses EDA tools to initially design and subsequently test the operation of the design using computer simulation techniques. With reference to FIG. 1, a typical computer logic simulation technique proceeds by initially providing a logic design in the form of a schematic or netlist stored in a file 10 and converting the netlist by means of a logic compiler 12 into a simulator logic netlist 14 that is used by a logic simulator 15. During simulation, a set of simulation input vectors 16 is also provided to the logic simulator, which reads the simulator logic netlist 14, along with the simulator input vectors 16 and simulates the operation of the logic design by propagating logic levels through the logic primitives. Simulator 15 generates a set of output vectors 18, which are the simulated outputs of the logic design.
With increasing complexity and capacity of the devices, using a schematic level netlist for design simulation is time consuming. Additionally, with increasing complexity, debugging the design at the schematic level is not intuitive, thereby increasing the time required for debugging and making the debugging process cumbersome.
Consequently, there is a need in the art for a design tool that will allow for faster simulation times and also allow for a more intuitive approach to debugging the design.